Furthermore, the proposed design has very high maximum operating frequency. This feature high maximum frequency will allow the design to be built in hardware applications which need very high speed DWT processor. Power consumption analysis: Power consumption is a vital design factor besides maximum operating frequency and hardware area. In addition to the low CLBs slices number and high operating frequency, the proposed design has very low power consumption. Table 4 shows the summary of the power consumption analysis for the proposed architecture for number of FPGA devices in different operating frequencies.

The quiescent power for each FPGA device represents the dominated part of the total consumption power. It is for the whole device including idle FPGA resources. This makes the proposed design very suitable for using in low power applications such as mobile and wireless multimedia sensor networks.

The implementation tests are achieved by employing the FIL tool which is used to provide an interface between PC and on chip device through Ethernet cable. Figure 6 shows the model that was used in the tests. The model consists a one bit counter free running which used as external clock. The input samples X1 and X2 are either entered from row selector which forward two samples each clock cycle, or from workspace memory of IHLWT coefficients depending the operating mode.

The selection of the input buses has been achieved by manual switches as shown in Fig. The core on chip has been tested by using audio signals as input in both real time recording and signal from Matlab work-space. Various sampling frequencies of audio signal are used in tests 8, 16 and Figure 7 shows a sample of the tests 5 sec audio signal with 8 kHz sampling frequency in forward mode.

Comparison with some of the related works: Table 5 shows a comparison between the proposed design and some of that of the literatures. In the table, comparisons for the most important factors in the hardware design such as the required components for the processor, processing speed, DWT design mode, control complexity and critical path delay. The table shows superior of the proposed design over the others in most features. Very simple circuit, requiring only one adder and subtractor with two simple proposed shifters, is used for both forward and inverse transformations. The proposed shifter circuit is only represented by a simple wiring circuit.

It is used to compute floor and multiplication operation in a one simple step. The overall design is very simple and generic. It can be effortlessly configured to process one dimension signal for various signal lengths. Many real time audio recording tests have been performed for the on-chip device to process in both forward and inverse modes. All the results obtained have been identical when compared to the Matlab software results. Subscribe Today. Science Alert. All Rights Reserved.

Research Article.

Similar Articles in this Journal. Search in Google Scholar. Journal of Applied Sciences, DOI: One level decomposition and reconstruction of lifting wavelet transform LWT , a Forward lifting scheme and b Inverse lifting scheme. It performs in-place operation calculation.

Hence it does not require any extra memory to save its outputs.

General architecture of the proposed design. Comparison between the proposed and some of the literatures for one dimension discreet wavelet transform DWT architectures. Altermann, J. Costa and S. Almeida, High performance Haar wavelet transform architecture. Andra, K. Chakrabarti and T. Acharya, A VLSI architecture for lifting-based forward and inverse wavelet transform. IEEE Trans. Signal Process.

Masselos, P. Cheung and Y. Andreopoulos, Pham, Efficient parallel architecture for multi-level forward discrete wavelet transform processors. VLSI implementation for one-dimensional multilevel lifting-based wavelet transform. Eshghi, Implementing a new architecture of wavelet packet transform on FPGA transform with tree structure.

Huang, C. Tseng and L. Chen, VLSI architecture for forward discrete wavelet transform based on B-spline factorization. Signal Image Video Technol. Niijima and S. Takano, FPGA-based lifting wavelet processor for real-time signal detection. Mandal and B. Cockburn, Efficient architectures for 1-D and 2-D lifting-based wavelet transforms. Namane, VLSI design for high-speed image computing using fast convolution-based discrete wavelet transform.

Mallat, S. A theory for multiresolution signal decomposition: The wavelet representation. Pattern Anal. Chauhan, FPGA design of speech compression by using discrete wavelet transform. Shi, G. Liu, L. Zhang and F. Li, An efficient folded architecture for lifting-based discrete wavelet transform. Circuits Syst. However, since the technique involves intensive cross-correlation computation between a pre-selected QRS template and the raw ECG data, such a heavy computational burden could also undesirably restrict its use to quite a limited number of applications [ 2 ].

In fact, there actually exist a number of different types of other possible techniques for noise reduction. Among these methods, the wavelet based de-noising has been considered as one of the most effective techniques [ 3 ]. Since decades ago, wavelet-based methods have been widely used in biomedical signal processing [ 4 , 5 ].

In short, wavelet transforms represent the temporal characteristics of a signal by its spectral components in frequency domain.

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The theory of wavelet transforms asserts that signals to be analyzed can be decomposed into a variety of scales with different time and frequency resolutions using the so-called multi-resolution analysis algorithm [ 5 , 6 ]. Continued research investigations have addressed important issues across many applications spanning from data compression [ 7 , 8 ] to biomedical signal and image processing [ 9 , 10 , 11 , 12 ].

In addition to data compression, signal and image processing, it has been known that the wavelet transform-based technique can be also applied for the purpose of signal de-noising, as mentioned above. In this regard, the noise level can be effectively reduced while the sharp features or known noise characteristics of the signal can be well preserved [ 1 , 13 , 14 ]. For example, Du et al. In representing a signal that is contaminated by additive unstructured noise using discrete wavelet transform DWT , we may hypothesize that most larger wavelet coefficients may generally result from the signal portion, while the small-valued wavelet coefficients should be attributed to the noise portion which could possibly contaminate all wavelet coefficients.

Thus, reconstructing the signal from the thresholded wavelet coefficients would provide a de-noised version of the original signal. Therefore, the fact as indicated above leads to the idea of de-noising a noisy signal in its wavelet domain. In addition, the DWT based de-noising method has been also widely applied in biomedical signal analysis [ 16 , 17 , 18 ].

Ahsan et al. Although their results indicated that the performance of the model was satisfactory, the computational cost in time and memory complexity could be greatly enhanced if higher precision is demanded. However, in that work, the de-noising scheme was only realized in software manner. In this paper, a novel, simple, and reliable wavelet-based de-noising algorithm and its hardware realization for real-time medical signal preprocessing and analysis is presented.

This study mainly evaluated the proposed DWT de-noising method and its circuit architecture in both software and hardware manners. It is also worth noting that in such a circuit, the real-time implementation of DWT computation requires substantially smaller memory storage, as compared to that required by the direct computation of DWT, thus permitting a time- and memory-efficient architecture.

Simulation experiment results obtained from both the software and hardware simulations indicated that the proposed wavelet de-noising scheme could robustly and effectively reduce the noise level in a real-time manner. Figure 1 shows a schematic block diagram of the overall wavelet de-noising process.

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According to Figure 1 , the procedure of the wavelet de-noising scheme is briefly described as follows. First, the three-level, four-tap DWT of a noise-contaminated medical signal is computed. Next, a so-called thresholding process is applied to the DWT by throwing away the wavelet coefficients i.

The rationale behind the thresholding process is based on an assumption that the noise generally results in small-valued wavelet coefficients while the large coefficients should be mostly due to the actual signal. Then, the de-noised signal can be synthesized simply by computing the IDWT on the thresholded wavelet coefficients and thus the SNR of the de-noised signal is finally enhanced.

In short, the wavelet de-noising circuit to be designed here in this study mainly consists of three modules: a DWT, a thresholding, and an IDWT, which are respectively presented in the subsequent sections. In this section, a real-time DWT structure is briefly described. First, note that computing DWT in a real-time fashion with low memory complexity is desirable in many aspects of medical signal processing applications. On the other hand, being implemented by convolution, the DWT computation requires both a large number of arithmetic operations i.

Meanwhile, to achieve real-time wavelet de-noising, it is neither practical nor possible to directly compute the DWT for the entire signal that is supposed to be quasi-infinite in length. Fortunately, there were a number of efficient scalable VLSI Very-large-scale integration architectures for real-time computation of DWT developed previously [ 21 , 22 , 23 , 24 , 25 ]. Among all these efficient VLSI architectures, a structure referred to as the lifting-based scheme demands much fewer computations than do the conventional ones and thus has been proposed for the DWT implementation for the past several years [ 24 , 25 ].

However, since the lifting scheme can be only applied for constructing biorthogonal wavelets, it may not be well suited to our applications. Therefore, in this study an existing structure of one-dimensional 1D DWT decomposition developed by Yu et al. Unlike the lifting based scheme, the DWT architecture we adopted here can be applied for constructing any wavelet filters. A three level 1D DWT structure as developed in [ 21 ]. Note that since here the Daubechies 4 filters were adopted, H z and G z denote a 4-tap lowpass and highpass filters, respectively, where.

According to [ 21 ], computations of all the wavelet coefficients after the second level can be folded into the second stage filter bank in Figure 2 by interleaving the computations of the second level with those of the remaining levels note that there are three dyadic levels in this study. Such an operation scheduling approach results in the architectures of the first and second stages for realizing the decimation filter process G z as indicated in Figure 3 and Figure 4 , respectively.

Similarly, H z filtering operations can be realized in the same way. The first stage architecture of the 1D DWT as developed in [ 21 ]. The second stage architecture of the 1D DWT as developed in [ 21 ]. As stated previously, given a raw measured signal, in order to effectively reduce the noise level and simultaneously preserve the sharp features of the signal, a deliberately designed thresholding stage needs to be incorporated into the de-noising circuit.

In this study, a novel adaptive thresholding scheme was devised. Such a thresholding process is applied to the wavelet coefficients generated from the DWT module for reducing the noise level while preserving the sharp features of the signal. It should be noted that there was an adaptive threshold assigned for each DWT level or dyadic level and used to perform the thresholding process on the wavelet coefficients generated at that level.

## Front End Design(VHDL/Verilog HDL)

Here, the adaptive threshold applied for the j -th dyadic level is defined as. Obviously, the thresholds used for different levels were all related one another because according to Equation 2 they were all determined using the wavelet coefficients at the 1st level. In order to explain the calculation of the thresholds more clearly, first we consider the threshold for the 1st level i.

Here, 32 is an empirical choice of the moving window length. Furthermore, according to Equation 2 we then have. That is, the threshold would be elevated by a factor of 2 as the dyadic level is increased by 1. Therefore, the threshold th j i is updated every 32 first-level wavelet coefficients. Also note that since the scaling factor i. Moreover, the thresholding scheme can be formulated as. Note further according to Equations 2 and 6 , one may see that the threshold is applied and updated in a block-wise manner.

Figure 5 shows the architecture of the proposed thresholding circuit. Three computation paths respectively filter three level data i. The threshold calculation consists of two steps described as follows. First, the average of the absolute values of 32 consecutive wavelet coefficients at the first level is computed using an ABS averaged circuit. The thresholds used for all the three computation paths, denoted as th 1 i , th 2 i , and th 3 i , can be then obtained by right shifting 4-bit, 3-bit, and 2-bit, respectively. Note further that due to the algorithmic regularity, the proposed thresholding architecture can be easily scaled up with the block size and the number of dyadic levels.

In fact, the computation of all the scaling or coarse coefficients over all levels can be folded into the first stage filter bank as shown in Figure 6. This folded structure is illustrated in Figure 7. Moreover, given the first level scaling and thresholded wavelet coefficients, the de-noised signal is then synthesized at the second stage filter bank, as illustrated in Figure 8. With a switch-based connection of the architectures of Figure 7 and Figure 8 , the IDWT module derived for this research would work perfectly in accordance with the preceding DWT and thresholding modules to produce the de-noised signal in a real-time manner.

Figure 9 depicts a schematic block diagram illustrating how the DWT, the thresholding, and the IDWT modules connect to perform the de-noising function. Note that the output of the circuit is switched between the scaling coefficient input of this circuit itself and the coarse coefficient input of the next stage circuit i. In addition, it should be also noted that there are a number of thresholded wavelet coefficients obtained after applying the thresholding process throughout all the levels waiting to be input into the IDWT module, and thus, one may expect that the number of registers required for the implementation of the wavelet de-noising algorithm as shown in Figure 9 would be greatly increased.

Therefore, the focus of the next step design is on minimizing the number of registers used in the circuit so the chip size due to the registers remains optimally small. For this purpose, here a lifetime analysis used to systematically evaluate the minimum number of registers was further adopted. That is, after the minimum number of registers required for the implementation of the circuit was determined, a technique, referred to as the forward-backward register allocation, was then used for allocating the intermediate thresholded wavelet data to these registers [ 26 , 27 ].

To evaluate the performance of the proposed de-noising algorithm as well as to demonstrate its noise reduction capability under a field programmable gate array FPGA design, simulation experiments were conducted in both software and hardware manners. It should also be noted that since a practically measured ECG signal is mainly composed of actual cardiac activity and noise due to various sources, such as electromyogram EMG , power-line interference and motion artifacts.

In this performance evaluation task, we consider the de-noising performance upon the white Gaussian noise first, and then upon the 60 Hz power interference when combined with white Gaussian noise, which can be thought of as being a more realistically encountered type of noise. The sampling rate of the ECG signal was Hz. Figure 10 shows an example of the simulated Gaussian noise corrupted ECG signal used in this performance validation task. Apparently, the de-noised signal as shown in Figure 11 looks much cleaner and thus, most of the important features or components of ECG may be clearly observed, indicating that the wavelet de-noising could faithfully and robustly recover the desired ECG signal from the noise-contaminated situation.

Figure 12 shows the hardware simulation results.

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The fixed-point word length of the circuit was set to 11 bits plus one sign bit. In fact, the correlation coefficient between both the software and hardware de-noised ECG signals is over 0. It provides a hardware-software co-design, co-simulation, and co-verification environment and is thus very suitable for a complete application specific integrated circuit ASIC logic emulation, prototyping verification and IP development.

In such a hardware experimental platform, we imported the input signals from PC into our designed circuit on the FPGA of VeriEnterprise and exported the output signals to PC for observation. Consequently, the de-noised ECG signal generated by the FPGA module was exactly the same as that obtained from the hardware simulation results as depicted in Figure Since, as stated previously, raw ECG usually presents different kinds of noise sources such as EMG, 60 Hz power-line interference, and motion artifacts, only white Gaussian noise used in the performance evaluation may limit the extent and scope of the investigation.

Thus, it is necessary to include other noise types in the performance evaluation. Here, simulation results of a mixed 60 Hz power line interference and Gaussian noise reduction are presented. Similarly, given the same noiseless ECG signal, a simulated 60 Hz power interference mixed with white Gaussian noise-contaminated ECG signal was thus composed, as depicted in Figure Figure 14 and Figure 15 present the appearances of the de-noised output signals produced by the software and hardware simulations, respectively.

## CiNii Books - VLSI design of wavelet transform : analysis, architecture, and design examples

Similarly, observing either Figure 14 or Figure 15 , one may see that most of the important features of ECG were preserved, thus indicating that the wavelet de-noising could still robustly recover the desired ECG signal from the noise-contaminated situation, even under the presence of the 60 Hz power-line interference. De-noised ECG signal obtained after suppressing mixed noise by software simulation.

De-noised ECG signal obtained after suppressing mixed noise by hardware simulation. In order to understand how the SNR affects the performance of the proposed DWT based de-noising architecture, we experimentally studied its de-noising performance on a set of simulated noisy ECG signals at a variety of SNR levels ranging from 0 to 12 dB.

Both the de-noising algorithmic and its architectural performances were evaluated against all these simulated ECG measurements with different SNR values. That is, we tested and examined the capability of the proposed DWT de-noising in its software and hardware realizations. It is defined as the percentage of the magnitude-squared difference between the noiseless ECG and the de-noised ECG, that is,. In addition, a similar metric typically used for quantitatively evaluating the de-noising performance, called the percent root mean square difference PRD can be also used for the performance evaluation [ 28 , 29 ].

Observing the results as shown in Figure 16 , one may see that the as expected, the PEE values evaluated on the original noise-contaminated ECG signals were all greater than those evaluated on the de-noised signals, regardless of being derived in hardware or in software manner. Also, one may notice that the software realization substantially outperformed the hardware one. This is because the former leads to the floating-point representations while the latter is in fixed-point implementation.

In our case, the fixed-point word length was set to 12 bits. In fact, in hardware realization the desire for fine quantization i. We further compared the performance of our de-noising algorithm and circuit, as shown in Table 1 , with respect to an existing method, as proposed in a previous work [ 28 ], based on PRD. Obviously, the proposed de-noising algorithm and its circuit both achieved much better de-noising performance than did the one as proposed by [ 28 ].

SNR versus the PEE values obtained before applying wavelet de-noising, after applying software- and hardware-based wavelet de-noising, respectively, i. Note that in order to make a performance comparison between the proposed method and its circuit and an existing de-noising method [ 28 ], we here also included the percent root mean square differences PRDs when SNR levels were at 6 dB and 10 dB, respectively. Furthermore, we also experimentally studied the de-noising performance on a set of simulated 60 Hz power interference and Gaussian noise-contaminated ECG signals at different SNR levels ranging from 0 to 12 dB and all the numerical results of PEE obtained at different SNR levels were depicted in Figure 17 and tabulated in Table 2.

Similarly, we further compared the performances of our de-noising algorithm and circuit respectively, with respect to the existing method [ 28 ] based on PRD. As a result, the proposed de-noising algorithm and its circuit still showed much better de-noising performance than did the one as proposed by [ 28 ]. Finally, in order to further demonstrate the proposed design, the Synopsys Design Compiler was also applied with an Artisan TSMC 40 nm standard cell library to implement the entire de-nosing system. The performance characteristics of the integrated circuit IC synthesis simulation are as listed in Table 3.

Performance characteristics of the IC synthesis simulation for the proposed de-noising system design. In this paper, the implementation of a real-time DWT based signal de-noising algorithm is introduced. The aim of this study is to devise and realize a digital signal processing DSP architecture associated with the wavelet de-noising scheme, thus ensuring and enhancing the microelectronic reliability for signal integrity in the system-level medical devices or products of interest. The proposed wavelet based de-noising architecture is constructed by a cascade combination of three modules: a DWT, a thresholding, and an IDWT.

Simulation experiment results obtained after performing both the software and hardware simulations on the task of ECG de-noising demonstrated the feasibility of the proposed DSP architecture. In addition, one may see that the circuit could not only meet the requirement of real-time processing, but also effectively reduce the noise level associated with the ECG signal while the sharp features or components of the medical signal can be faithfully preserved.

Finally, we successfully implemented it on a commercial FPGA chip for prototyping and real-time applications.