The above objectives of reducing error due to charge injection and improving linearity is provided in a differential embodiment of the circuit and method of the present invention. The above-described double-sampled switched-capacitor circuit is effectively duplicated for each negative feedback output-input pair of the differential amplifier e. The two double-sampled switched-capacitor circuits are referenced to each other rather than a ground node, providing fully differential operation that cancels error due to charge injection to the degree of symmetry of the charge-injection magnitude e.
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The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings. Referring now to the figures, and in particular to FIG.
An input voltage Vin is alternatively applied to a first capacitor C 11 or a second capacitor C 13 via switches S 11 and S 12 to sample an input signal. When capacitor C 11 is selected for sampling, switch S 17 is closed, grounding a second terminal of capacitor C 11 , similarly switch S 18 grounds a second terminal of capacitor C 13 , when capacitor C 13 is selected for sampling. The capacitor C 11 or C 13 that is not selected for sampling is connected via switches S 13 and S 15 for C 11 or switches S 14 and S 16 for C 13 in the feedback path of an amplifier A 11 , which provides a sampled output Vout.
The control signals for switches S 11 -S 18 are provided by buffer B 11 and inverter I 11 so that two complementary phases of the sampling clock signal are provided for selecting the alternate states required for switches S 11 -S The circuit of FIG.
VM, CM, and HM Compensation
With further reference to FIG. As can be seen from the diagram at the top of the figure, amplifier A 11 output Vout has a step characteristic that follows the shape of input signal Vin. Note that the Vout signal is delayed by one-half of the sample clock period, as the sampled value is not transferred to the amplifier A 11 output until the alternate state of the sample clock.
Note that the sampled waveform is also delayed by one-half of the sampling interval, but contains half as many steps, as the input sampled value is only transferred to the amplifier once per sample clock period. The result is that transitions of the sampled waveform such as transition 23 are larger than the transitions of the Vout signal of the present invention such as transition 21 for signals approaching the Nyquist frequency i. Therefore, the circuit of FIG.
The output signal taken during either phase of sample clock, but not both. Referring now to FIG. Switch transistors N 31 and N 32 control placement of capacitor C 31 in the input sample position, while switch transistors N 33 and N 34 control placement of capacitor C 31 in a feedback path of amplifier A 31 in this case, the negative feedback path between the non-inverted output and the inverting input of amplifier A Similarly capacitor C 33 , which samples in alternation with capacitor C 31 in a manner similar to the operation of the circuit of FIG.
Bootstrap clock circuits 31 A-B provide control of input switch transistors N 31 and N 35 , so that linearity is improved as described below, and bootstrap clock circuits 31 E-F, provide control of switch transistors N 34 and N 38 , also reducing non-linearity resulting from differences between steps in the output signal of amplifier A At the bottom of FIG. Switch transistors N and N control placement of capacitor C 37 in the input sample position, while switch transistors N and N control placement of capacitor C 37 in the other feedback path of amplifier A 31 the negative feedback path between the inverted output and the non-inverting input of amplifier A Similarly capacitor C 35 , which samples in alternation with capacitor C 37 , is placed in the input sample position by activation of switch transistors N and N , while transistors N and N control placement in the above-described other feedback path of amplifier A Bootstrap clock circuits 31 C-D provide control of input switch transistors N and N , and bootstrap clock circuits 31 G-H, provide control of switch transistors N and N Rather than referring the input signal to ground as in the non-differential circuit of FIG.
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Switch transistors N 32 , N 36 , N and N couple their respective capacitors as described above to this common-mode reference, rather than ground. Also, Switch transistors N 39 and N 40 , are activated to further reduce any differences between the common-mode voltage as applied to the common-mode terminal of capacitors C 31 and C 37 by transistor N 39 and capacitors C 33 and C 35 by transistor N 40 , when the associated capacitors are selected for sampling the input. Referring also to FIG.
The c-phase clock signal is the clock signal for the opposing sampling phase, used because it is valid for a window within the period while the d-phase clock signal is deasserted. The gate of an external transistor e.
Prior to assertion of the c-phase clock signal, capacitor C 41 is charged to Vdd through transistor N 51 and transistor N 52 when the d-phase clock signal is deasserted. Transistor N 52 which couples the terminal of capacitor C 41 opposite transistor N 52 to ground until the c-phase clock signal is asserted, at which time capacitor C 41 is fully charged to Vdd. Simultaneously, the raised voltage level is applied to the gate of the external transistor through transistor P 51 and when the d-phase clock is deasserted, transistors N 53 , P 52 and P 51 are turned off and the gate of the external transistor is left floating.
At the end of the phase-c signal, a transistor N 54 completely turns off the gate of the external transistor. Referring further to FIG. Buffers B 51 -B 54 forms a buffer chain that receives the sample clock input and generate four phases of a sampling clock for a first sampling phase, consecutively delayed by the delays of the buffer chain.
Demystifying Switched-Capacitor Circuits Vol. 1 by Mingliang Liu (2006, Paperback)
Inverter I 51 inverts the c-phase clock and delays it by the same delay as provided by buffer B 54 , providing a complementary d-phase signal. Buffers B 55 -B 58 form a second buffer chain providing four clock phases for a second sampling phase and inverter I 52 provides an inverted version of the second d-phase signal.
The timing relationships of the clock generator signals are as depicted in FIG. While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form, and details may be made therein without departing from the spirit and scope of the invention. A method of sampling an input voltage, comprising: alternating a first capacitor between a first sampling position for charging said first capacitor to said input voltage and a first hold position for holding an output voltage of an amplifier; and.
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Mingliang Liu , Michael Liu. This book helps engineers to grasp fundamental theories and design principles by presenting physical and intuitive explanations of switched-capacitor circuits. Numerous circuit examples are discussed and the author emphasizes the most important and fundamental principles involved in implementing state-of-the-art switched-capacitor circuits for analog signal processing and power management applications.
Throughout the book, the author presents numerous step-by-step tutorials and gives practical design examples.
While some quantitative analysis is necessary to understand underlying concepts, tedious mathematical equations and formal proofs are avoided.
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